1. Field of the Invention
The present invention relates in general to the data processing systems. In one aspect, the present invention relates to a method and apparatus for memory initialization during system boot.
2. Description of the Related Art
Data processing or computing systems are designed to give independent computing power to one or more users, and can be found in many forms including, for example, mainframes, minicomputers, workstations, servers, personal computers, internet terminals, notebooks and embedded systems. In general, computer system architectures are designed to include provide one or more microprocessor cores with high speed, high bandwidth access to selected system components, associated memory and control logic (typically on a system board) and a number of peripheral devices that provide input and/or output (I/O) for the system. For example, FIG. 1 illustrates an example architecture for a conventional computer system 100. The computer system 100 includes one or more processors 102 connected across a “north” bridge 104 to a system memory 108. Typically, the memory array 108 includes one or more memory modules, and may also include memory slots for the addition or replacement of memory modules. The north bridge circuit 104 can be programmed to interface to a variety of memory modules, and as illustrated, the north bridge circuit 104 is shared among a plurality of memory modules 108. As a result, if differing memory modules are populated, the north bridge circuit 104 must be programmed with parameters that allow each memory module to operate correctly. The depicted north bridge circuit 104 is connected over a high-speed, high-bandwidth bus (e.g., a memory bus 107) to the memory 108, and is also connected over a high-speed, high-bandwidth bus (e.g., an Alink or PCI bus) to a “south” bridge 112. The “south” bridge 112 is connected to one or more I/O devices, such as a Peripheral Component Interconnect (PCI) bus 110 (which in turn is connected to a network interface card (NIC) 120), a serial AT Attachment (SATA) interface 114, a universal serial bus (USB) interface 116, and a Low Pin Count (LPC) bus 118 (which in turn is connected to a super input/output controller chip (SuperI/O) 122 and BIOS memory 124). As will be appreciated, it will be appreciated that other buses, devices, and/or subsystems may be included in the computer system 100 as desired, such as caches, modems, parallel or serial interfaces, SCSI interfaces, etc. Also, the north bridge 104 and the south bridge 112 may be implemented with a single chip or a plurality of chips, leading to the collective term “chipset”. Alternatively, all or some of the functionality of the bridge chips may be present within processor 102.
Computer systems typically include a set of built-in software routines called the basic input/output system (BIOS) which provides a software interface between the system hardware and the operating system software so that the programmer and user can interact with the system hardware. The BIOS instructions are stored in non-volatile memory 124 (e.g., ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically Erasable PROM), flash RAM (Random Access Memory), or the like), and are used to control important computer system functions at power up, including testing and initializing memory, inventorying and initializing the system, and testing the system. These functions at power up are referred to as “system boot” or “booting the system” and can occur every time the system powers up or is reset. In the conventional computer system 100 shown in FIG. 1, the BIOS executes on one of the processors 102, referred to as the boot strap processor, to boot the computing system 100. In operation, the boot strap processor 102 communicates through north bridge 104 to the memory array 108. The north bridge circuit 104 includes a memory controller 106 that is connected to one or more channel controllers that interface with the memory bus 107, such as a double data rate (DDR) bus. The north bridge circuit 104 also communicates with one or more south bridges 112 on a standard bus 109, for example, a peripheral component interconnect (PCI) bus. South bridge 112 communicates to one or more input/output (I/O) devices 120, 122, 124, though additional or fewer devices (not shown) can be attached to the south bridge 112.
Upon system initialization, the boot strap processor 102 performs all memory testing and clearing during system boot which can take a significant amount of time. Large server systems often take several minutes to boot while the other processors are idle. In the depicted example, the BIOS executing on the boot strap processor initializes the memory controller 106 north bridge circuit 104 by programming registers from the boot strap processor 102 based on information from the DIMM memory 108 on the DDR memory bus 107. Memory initialization can include verifying population of memory modules, verifying proper operation of the memory (no stuck bits), and initializing or clearing the memory to known values. With large memory 108 (e.g., 8, 16, or 32 Gigabytes of memory), conventional systems can take several minutes to initialize the memory, especially where the “DDR training” processes use the boot strap processor 102 to initialize memory by consecutively executing an ordered sequence of memory initialization tasks without regard to dependency between tasks. This delay is exacerbated when there are large amounts of memory 108 attached to each controller 106.
Accordingly, a need exists for an improved memory initialization device, methodology and system which addresses various problems in the art that have been discovered by the above-named inventors where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.